This application claims priority to Japanese Patent Application No. JP 2001-164672, filed on May 31, 2001, the disclosure of such application being herein incorporated by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having wiring formed thereon.
2. Description of the Related Art
With miniaturization of integrated circuits for semiconductors, the minimum line width and the minimum spacing of wiring of element connection wirings have become narrower than before. If current density of wiring increases with further miniaturization of wiring, atomic migration may occur in the wiring material due to electric charge moving at high speed, so that breaking of the wiring, high resistance of the wiring and the like may possibly occur. Consequently, the wiring thickness cannot be made thinner to suppress an increase in current density, thus causing such problems as faulty processing of wiring as a result of an increase in the wiring aspect ratio and an increase in parasitic capacity due to a decrease in wiring spacing.
In order to alleviate these problems, it is considered to take such steps as changing from conventional aluminum to copper as a wiring material, reducing a wiring resistance, and improving migration-resistance properties.
In addition, with regard to a method of forming wiring, it is proposed to employ a damascene method in which a wiring groove is hollowed out in an insulating film so as to embed the wiring itself in the insulating film to reduce faulty processing of wiring and a parasitic capacity due to reduction of the wiring spacing.
The damascene method is a method of forming wiring by hollowing out a wiring groove in an insulating film and embedding the wiring itself in the insulating film.
FIG. 2 schematically illustrates a conventional process of forming connection wiring: FIG. 2A showing a wiring groove forming process; FIG. 2B showing a wiring material layer forming process; FIG. 2C showing a polishing process; and FIG. 2D showing a copper wiring forming process.
As for the process of FIG. 2A, after an element (not illustrated) is formed on a silicon substrate, silicon oxide films 11 and 12 which are insulating films are formed in sequence, and a photo resist is coated on the films, whereafter an aperture is made by photolithography at a photo resist portion which becomes wiring, thus forming a photo resist pattern. Next, using the photo resist pattern as a mask, the silicon oxide film 12 is subjected to anisotropic etching, thereby forming a wiring groove 13a of a wide line width and a wiring groove 13b of a narrow line width on the silicon oxide film 12 and forming a conductor pattern.
As for the process of FIG. 2B, after forming tantalum nitride 14 as a first barrier metal layer on the conductor pattern, copper 15 is formed as a wiring material layer. At this event, the copper 15 formed on recesses of the conductor pattern has its height of the surface formed lower than other portions.
As for the process of FIG. 2C, the copper 15 is polished until the nitride tantalum 14 is exposed.
As for the process of FIG. 2D, the tantalum nitride 14 and the copper 15 are polished until the silicon oxide film 12 is exposed, so that copper wiring is formed in the wiring grooves 13a and 13b. 
However, the height of the surface of the copper 15 formed on the wiring groove 13a on its wider line width is formed lower than other portions, and further, a condition of polishing the copper 15 is such that a polishing rate of the tantalum nitride 14 is slower than a polishing rate of the copper 15, wherefore after the tantalum nitride 14 is exposed, a phenomenon called xe2x80x9cdishingxe2x80x9d occurs due to the elasticity of a polishing cloth. As a result, as for the copper 15 formed in the wiring groove 13a, polishing proceeds from the surface of the exposed silicon oxide film 12 to the inside to cause the wiring film thickness to be reduced. Consequently, there may occur problems such as an increase in wiring resistance and degradation of flatness or smoothness.
The present invention has been conceived in view of the aforementioned problems in the prior art and it is preferable according to a preferred embodiment of the present invention to provide a manufacturing method for a semiconductor device which forms wiring having uniform film thickness.
According to a preferred embodiment of the present invention, there is provided a manufacturing method for a semiconductor device under which wiring is formed. The method includes forming wiring grooves in an insulating film to form a conductor pattern, forming a first barrier metal layer and a wiring material layer on the conductor pattern, forming a second barrier metal layer so that a height of the surface of the first barrier metal layer on protuberances of the conductor pattern is equal to a height of the surface of the second barrier metal on recesses of the conductor pattern, removing the second barrier metal layer on the protuberances of the conductor pattern, removing the wiring material layer on the protuberances of the conductor pattern, and removing the first barrier metal layer on the protuberances thereof and the second barrier metal layer on the recesses thereof.
In a construction described above, the wiring grooves are formed in the insulating film to form the conductor pattern, the first barrier metal layer and the wiring material layer being formed on the conductor pattern, the second barrier metal layer is formed to make the height of the surface of the first barrier metal layer on the protuberances of the conductor pattern equal to the height of the surface of the second barrier metal layer on the recesses of the conductor pattern, so that when the second barrier metal layer and the wiring material layer are removed until the first barrier metal layer is exposed, the wiring material layer in the wiring grooves is protected by the second barrier metal layer on the recesses of the conductor pattern, thus assuring the wiring material layer in the wiring grooves is not removed deeper than the surface of the insulating film and no decrease of the wiring film thickness is caused.